It is an advantage to use advanced methods for verification to ensure fully operational design, and to save time by reuse of existing tools while getting a high degree of test design coverage.
Some of the existing tools for use in VHDL design is Universal VHDL Verification Methodology (UVVM) and Open Source VHDL Verification Methodology (OSVVM), whereby it is possible to control stimuli in an easy way, and report test coverage.
Code and functional coverage, and different formal test methods, can be used in addition.
Reference models, written in for example Python or C, can also be an efficient way to test if a design is implemented correctly, in special for complex protocol analysis and mathematical models.
Test benches are written as self checking test benches, so it is easy to reuse these as part of a large regression, whereby it can be checked that all existing modules operate correctly also after updates.
Review of design
Review of existing design can be performed, in order to ensure high quality in the design, or find suggestions for design or test improvements.
It can also be an advantage to make review if there are known problems in the design, or to get multiple developers involved in a critical part of the design.