Experience with technologies below, and numerous others not mentioned, so ask for specific requirements.
Major FPGA brands and the related tools for:
Creation of architectural model, based on mathematical descriptions, and high level design principles, in order to determine architecture and estimate resource for resulting design.
Ethernet and similar packet based communication
Architecture, design, and implementation of Ethernet and similar packet based communication systems, using SERDES technology and various IP blocks and custom design, for decoding at various ISO layers and deep packet inspection.
Mathematical operations on high-speed image streams, applying operations like convolution matrix, conversion through tables, bilinear-interpolation, and perspective correction.
Embedded CPU system design, implementation and interface, with distributed bus connections for custom modules.
DDR memory interface
Architecture, design, and implementation of DDR memory interface, for various DDR revisions. These interface are usually implemented through the specific hard IP block available in the FPGA brand, and the PCB interface must be made correct for reliable high speed operation.
Asynchronous design and Clock-Domain-Crossing (CDC)
Asynchronous design and Clock-Domain-Crossing (CDC) implementation is a small but crucial design part of the system, and can result in sporadic and tough bugs if not implemented correctly.
Static Timing Analysis (STA) and timing closure
Timing analysis of the finished design is required for reliable operation across voltage, temperature and process ranges.
Proven design methodology
Use of well-defined and proven design methodology results in a predictable design implementation with fewer bugs.
High level verification
Verification quality can be increased and the time can be reduced significantly through use of high level verification, through use of for example regressions tests, advanced test benches, self-checking tests, assertion based verification, random stimuli, and reference models.
Automating synthesis and verification
Running the synthesis and verification using self checking and automated scripts speeds up repeated runs, with the advantage that less error-prone human interaction is made :-)