Experience with tools below, and numerous others not mentioned, so ask for specific requirements.

Hardware Description Language (HDL)

  • VHDL
  • Verilog
  • SystemVerilog

Synthesis tools

  • Intel (Altera) Quartus with Qsys
  • Xilinx ISE and Vivado
  • Lattice Diamond

Static Timing Analysis (STA)

  • Synopsys PrimeTime
  • Intel (Altera) TimeQuest
  • FPGA native tools for e.g. Lattice


  • Mentor ModelSim
  • Aldec Riviera-PRO and Active-HDL
  • Xilinx ISim
  • Synopsys VCS

Verification languages and frameworks

  • Open Source VHDL Verification Methodology (OSVVM)
  • SystemVerilog
  • Assertion based simulation
  • Aldec ALINT

C code

  • Applications for embedded CPU
  • Drivers
  • Reference modeller for test

 Scripting for automatizing

  • Python
  • Tcl
  • Make


  • Revision control: Git and Subversion (SVN)